The present invention pertains to circuitry for the protection of the contents of dynamic memory and more particularly to circuitry for preventing premature termination of a bus access cycle to dynamic memory by a central processing unit (CPU).
Computer control via central processing units (CPUs) of real time switching operations in modern telephone central offices is well known. In recently developed telephone central offices, the CPU control function has been provided by a number of small CPUs acting together. Such CPU arrangements are termed distributed processing systems.
In distributed processing systems, it is required that the CPUs interact directly with one another. In order for the CPUs of the distributed processing system to interact with one another, they must have communication via data transmission. One method of achieving this data transmission involves each CPU ceasing any other tasks which it may be performing; establishing a direct link via a predefined protocol scheme; and, transmitting the required data between one another.
A more efficient method for CPU communication involves asychronously placing information in a predefined resource, such as memory, so that the CPU which is to receive the information may remove the information at a particular time convenient for it to do so which is shown in U.S. Pat. No. 4,376,975. This is typically accomplished through a common memory scheme in which a number of CPUs access one particular memory.
Dynamic RAM memory may be employed to fulfill the needs of a common writable/readable memory. These dynamic RAM memories are periodically maintained by means of a refresh signal supplied to the memory under control of the CPU. Noise on this refresh lead may provide destruction of the contents of the dynamic RAM memory. In a system where duplex memory units are employed, such as telephone central offices, destruction of both copies of the RAM memory may occur. This noise may occur when a CPU is prematurely removed from the bus before completing its memory access cycle. This type of problem may also be caused by a number of other faults, all of which will result in a central office outage. This outage may require a complete reload of millions of words of CPU instructions and data. This may take considerable time, such as 30 minutes.
Due to the public policy requirement of providing continuous 24-hour a day telephone service to subscribers, such central office outages of 30 minutes would be unacceptable.